MEC1404 Datasheet, PDF (256/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
16.8 Low Power Modes
The 8042 Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
16.9 Description
16.9.1 BLOCK DIAGRAM
FIGURE 16-2:
BLOCK DIAGRAM OF 8042 Emulated Keyboard Controller
Host
Access
LPC I/O Index =00
Write Data
W
D7
LPC I/O Index =04
Write CMD
R
LPC I/O Index =00
D7
Read Data or AUX Data
R
D7
LPC I/O read index =04h
UD
AUXH = 1 Bit [5] is AUXOBF
AUXH = 0 Bit [5] is UD
2 _{IBF SET on Host Write to LPC I/O}
Index =00h or 04h
D7
IBF Cleared on EC Read to SPB
AUXH
Offset = 00h
3 _{OBF SET on EC Write to}
SPB offset = 100h or 10Ch
OBF Cleared by Read 0f
LPC I/O Index 00h
D7
RES
D6
RES
HOST_EC Data register
D6
D5
D4
D3
D2
EC_HOST Data Register
D6
D5
D4
D3
D2
Status Register
D6
D5
D4
UD
AUXOBF / UD
UD
D3
D2
C/D
UD1
Keyboard Control Register
D6
D5
D4
UD
OBFEN
UD
D3
D2
UD
PCOBFEN
PCOBF Register
D5
RES
D4
RES
D3
RES
D2
RES
D1
RES
D1
D0
D1
D0
D1
IBF2
D0
OBF3
EC
Access
R
SPB offset =100h
Read Data or CMD
W
SPB offset =100h
Write Data
SPB offset =10Ch
Write Aux Data
R
W
SPB offset =104h
D1
D0
SAEN
UD
R
W
FF_0508
D0
PCOBF4
WR
FF_0514
1 _{This bit is reset by}
LPCRESET and VTR_POR
4 _{PCOBFEN = 1 PCOBF is contents of Bit 0 SPB offset = 114h}
PCOBFEN = 0 PCBOBF is set on EC Write of SPB offset = 100 h
PCOBF is cleared on Host Read of LPC I/O index = 00h
16.10 EC-to-Host Keyboard Communication
The EC can write to the EC_HOST Data / AUX Data Register by writing to the HOST2EC Data Register at EC-Only
offset 0h or the EC AUX Data Register at EC-Only offset Ch. A write to either of these addresses automatically sets bit
0 (OBF) in the Status register. A write to the HOST2EC Data Register may also set PCOBF. A write to the EC AUX Data
Register may also set AUXOBF.
16.10.1 PCOBF DESCRIPTION
If enabled by the bit OBFEN, the bit PCOBF is gated onto KIRQ. The KIRQ signal is a system interrupt which signifies
that the EC has written to the EC2Host Data Register (EC-Only offset 0h). On power-up, PCOBF is reset to 0. PCOBF
will normally reflect the status of writes to EC2Host Data Register, if PCOBFEN is “0”. PCOBF is cleared by hardware
on a HOST read of the EC_HOST Data / AUX Data Register.
KIRQ is normally selected as IRQ1 for keyboard support.
Additional flexibility has been added which allows firmware to directly control the PCOBF output signal, independent of
data transfers to the host-interface data output register. This feature allows the MEC140X/1X to be operated via the host
“polled” mode. Firmware control is active when PCOBFEN is ‘1’. Firmware sets PCOBF high by writing a “1” to the
PCOBF field of the PCOBF Register. Firmware must also clear PCOBF by writing a “0” to the PCOBF field.
DS00001956D-page 256
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