MEC1404 Datasheet, PDF (149/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

6.11.11 QMSPI DESCRIPTION BUFFER 0 REGISTER
MEC140X/1X
Offset ^30h
Bits
Description
Type
31:16 TRANSFER_LENGTH
R/W
The length of the SPI transfer. The count is in bytes or bits,
depending on the value of TRANSFER_LENGTH_BITS. A value of
‘0’ means an infinite length transfer.
15:12 DESCRIPTION_BUFFER_NEXT_POINTER
R/W
This defines the next buffer to be used if Description Buffers are
enabled and this is not the last buffer. This can point to the current
buffer, creating an infinite loop.
11 DESCRIPTION_BUFFER_LAST
R/W
If this bit is ‘1’ then this is the last Description Buffer in the chain.
When the transfer described by this buffer completes the TRANS-
FER_COMPLETE status will be set to ‘1’. If this bit is ‘0’, then this
is not the last buffer in use. When the transfer completes the next
buffer will be activated, and no additional status will be asserted.
10 TRANSFER_LENGTH_BITS
R/W
1=TRANSFER_LENGTH defined in bits
0=TRANSFER_LENGTH defined in bytes
9 CLOSE_TRANFSER_ENABLE
R/W
This selects what action is taken at the end of a transfer. This bit
must be set only on the Last Buffer.
1=The transfer is terminated. The Chip Select de-asserts, the SPI
interface returns to IDLE and the DMA interface completes the
transfer.
0=The transfer is not closed. Chip Select remains asserted and the
DMA interface and the SPI interface remain active
8:7 RX_DMA_ENABLE
R/W
This bit enables DMA support for Receive Transfer. If enabled,
DMA will be requested to empty the FIFO until either the interface
reaches TRANSFER_LENGTH or the DMA sends a termination
request. The size defined here must match DMA programmed
access size.
1=DMA is enabled.and set to 1 Byte
2=DMA is enabled and set to 2 Bytes
3=DMA is enabled and set to 4 Bytes
0=DMA is disabled. All data in the Receive Buffer must be emptied
by firmware
Default
0h
Reset
Event
RESET
0h
RESET
0h
RESET
0h
RESET
1h
RESET
0h
RESET
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DS00001956D-page 149