MEC1404 Datasheet, PDF (355/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 24-6: DMA CHANNEL N REGISTER SUMMARY
Offset
24h
(Note 3)
28h
(Note 3)
2Ch
(Note 3)
Register Name (Mnemonic)
(Note 2)
DMA Channel N CRC Data Register
DMA Channel N CRC Post Status Register
DMA Channel N CRC Test Register
2: The letter ‘N’ following DMA Channel indicates the Channel Number. Each Channel implemented will have
these registers to determine that channel’s operation.
3: These registers are only present in DMA Channel 0. Offsets 20h to 2Ch are reserved in all the other chan-
nels.
24.11.1 DMA CHANNEL N ACTIVATE REGISTER
Offset ^00h
Bits
Description
7:1 Reserved
0 CHANNEL_ACTIVATE
Enable this channel for operation.
The DMA Main Control:Activate must also be enabled for this
channel to be operational.
Type
R
R/W
Default
-
0h
Reset
Event
-
DMA_
RESET
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DS00001956D-page 355