MEC1404 Datasheet, PDF (122/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 4-14: I/O BASE ADDRESS REGISTERS
Offset
Logical
Device
Number
(hex)
60h
C
Logical Devices
LPC Interface
(Configuration Port)
Reset Default
002E_0C01
(Note 1)
Base Address Register Bit Field Descriptions
Bits
Bits
Bits
[D31:D16] Bit [D15] Bit [D14] [D13:D8] [D6:D0]
Default
LPC I/O
Host
MASK
Address VALID DEVICE FRAME (Note 3)
002E
0
0
C
1
64h
0
EMI 0
0000_000F
0000
0
0
0
F
8042 Emulated
68h
1
Keyboard Controller 0060_0104
0060
0
0
1
4
6Ch
3
ACPI EC0
0062_0304
0062
0
0
3
4
70h
4
ACPI EC1
0066_0407
0066
0
0
4
7
74h
5
ACPI PM1
0000_0507
0000
0
0
5
7
78h
6
Legacy Port92/GateA20 0092_0600
0092
0
0
6
0
7Ch
7
UART 0
0000_0707
0000
0
0
7
7
80h
9
Mailbox Interface
0000_0901
0000
0
0
9
1
84h
A
ACPI EC2
0000_0A07
0000
0
0
A
7
88h
B
ACPI EC3
0000_0B07
0000
0
Port 80 BIOS Debug
8Ch
15
Port 0
0000_1500
0000
0
Port 80 BIOS Debug
90h
16
Port 1
0000_1600
0000
0
0
B
7
0
15
0
0
16
0
Note 1: The default Base I/O Address of the Configuration Port can be relocated by programming the BAR register for
Logical Device Ch (LPC/Configuration Port) at offset 60h.
Note 2: The FRAME and MASK fields for these Legacy devices are not used to determine which LPC I/O addresses to
claim. The address range match is maintained within the blocks themselves.
Note 3: The ACPI-ECx Mask bit field is a read/write bit field. All other MASK bit fields are read-only as defined in the register
description.
4.9.4 SRAM MEMORY BAR
Offset ^A0h
Bits
Description
31:0 LPC Host Address[31:24]
These 32 bits are used to match LPC Memory addresses
Type
R/W
Default
0h
Reset
Event
nSIO_
RESET
DS00001956D-page 122
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