MEC1404 Datasheet, PDF (402/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
29.8 Interrupts
This section defines the Interrupt Sources generated from this block.
Source
Description
PS2_ACT
PS2_DATx_WAKE
Interrupt request to the Interrupt Aggregator for PS2 controller instance
x, based on PS2 controller activity. Section 29.15.4, "PS2 Status
Register" defines the sources for the interrupt request.
Wake-up request to the Interrupt Aggregator’s wake-up interface for PS2
port x.
In order to enable PS2 wakeup interrupts, the pin control registers for
the PS2_DAT pin must be programmed to Input, Falling Edge Triggered,
non-inverted polarity detection.
29.9 Low Power Modes
The PS/2 Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.
The PS2 interface will only sleep while the PS2 is disabled or in Rx mode with no traffic on the bus.
29.10 Description
Each EC PS/2 serial channels use a synchronous serial protocol to communicate with the auxiliary device. Each PS/2
channel has Clock and Data signal lines. The signal lines are bi-directional and employ open drain outputs capable of
sinking 12m, as required by the PS/2 specification. A pull-up resistor, typically 10K, is connected to both lines. This
allows either the EC PS/2 logic or the auxiliary device to drive the lines. Regardless of the drive source, the auxiliary
device always provides the clock for transmit and receive operations. The serial packet is made up of eleven bits, listed
in the order they appear on the data line: start bit, eight data bits (least significant bit first), odd parity, and stop bit. Each
bit cell is from 60S to 100S long.
All PS/2 Serial Channel signals (PS2_CLK and PS2_DAT) are driven by open drain drivers which can be pulled to VTR
or the main power rail (+3.3V nominal) through 10K-ohm resistors.
The PS/2 controller supports a PS/2 Wake Interface that can wake the EC from the IDLE or SLEEP states. The Wake
Interface can generate wake interrupts without a clock. The PS/2 Wake Interface is only active when the peripheral
device and external pull-up resisters are powered by the VTR supply.
There are no special precautions to be taken to prevent back drive of a PS/2 peripheral powered by the main power well
when the power well is off, as long as the external 10K pull-up resistor is tied to the same power source as the peripheral.
29.11 Block Diagram
FIGURE 29-2:
PORT PS/2 BLOCK DIAGRAM
EC I/F
PS2_x
interrupt
48MHz
2 MHz
Control
Registers
State
PS/2
Machine Channel
PS2DAT
PS2CLK
DS00001956D-page 402
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