MEC1404 Datasheet, PDF (200/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
12.3 Signal Description
TABLE 12-1: SIGNAL DESCRIPTION TABLE
Name
nEMI_INT
Direction
OUTPUT
Description
Active-low signal asserted when either the EC-to-Host or the
Host_SWI_Event is asserted. This signal can be routed to nSMI
and nPME inputs in the system as required.
12.4 Host Interface
The registers defined for the Embedded Memory Interface (EMI) are accessible by the System Host and the Embedded
Controller as indicated in Section 12.10, "EC-Only Registers" and Section 12.9, "Runtime Registers".
12.5 Power, Clocks and Reset
This section defines the Power, Clock, and Reset parameters of the block.
12.5.1 POWER DOMAINS
Name
Description
VTR
The logic and registers implemented in this block reside on this single
power well.
12.5.2 CLOCK INPUTS
This block has no special clocking requirements. Host register accesses are synchronized to the host bus clock and EC
register accesses are synchronized to the EC bus clock, thereby allowing the transactions to complete in one bus clock.
12.5.3 RESETS
Name
Description
nSYSRST
This reset signal resets all the logic and register in this block.
12.6 Interrupts
This section defines the Interrupt Sources generated from this block.
EC-to-Host
Source
Host_SWI_Event
Description
This interrupt source for the SIRQ logic is generated when the EC_WR
bit is ‘1’ and enabled by the EC_WR_EN bit.
This interrupt source for the SIRQ logic is generated when any of the
EC_SWI bits are asserted and the corresponding EC_SWI_EN bit are
asserted as well. This event is also asserted if the EC_WR/EC_WR_EN
event occurs as well.
DS00001956D-page 200
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