MEC1404 Datasheet, PDF (13/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Note:
The numeric value appended to the end of the SMBus pins indicates they are 1.8V I/O signaling. E.g.
SMB03_DATA vs SMB03_DATA18. The SMB03_DATA signal uses standard 3.3V I/O signaling. The
SMB03_DATA18 signal operates at 1.8V I/O signaling levels.
6. SMBus Port pins can be mapped to any SMB Controller. The number in the SMBus signal names (SMBxx_DATA)
indicates the port value. E.g. SMB01_DATA represents SMBus Data Port 1
2.3 Notes for Tables in this Chapter
Note
Note 1
Note 2
Note 3
Note 4
Note 5
Note 6
Note 7
Note 8
Note 9
Note 10
Note 11
Note 12
Note 13
Note 14
Note 15
Description
The LAD and SER_IRQ pins require an external weak pull-up resistor of 10k-100k ohms.
The ICSP_MCLR pin is used to enable JTAG. There is an internal pull-up on this pin to keep it
from entering debug mode. When debug mode is entered the ICSP_DATA and ICSP_CLOCK
signals are automatically enabled on their respective pins. The System Board Designer should
leave the ICSP_MCLR pin as a no-connect.
An external cap must be connected as close to the CAP pin/ball as possible with a routing
resistance and CAP ESR of less than 100mohms. The capacitor value is 1uF and must be
ceramic with X5R or X7R dielectric. The cap pin/ball should remain on the top layer of the PCB
and traced to the CAP. Avoid adding vias to other layers to minimize inductance.
This SMBus ports supports 1 Mbps operation as defined by I2C. For 1 Mbps I2C recom-
mended capacitance/pull-up relationships from Intel, refer to the Shark Bay platform guide,
Intel ref number 486714. Refer to the PCH - SMBus 2.0/SMLink Interface Design Guidelines,
Table 20-5 Bus Capacitance/Pull-Up Resistor Relationship.
RESET_OUT# pin must be pulled to ground via an external 8.2k ohm resistor. This will ensure
the glitch-free tristate GPIO input will not glitch high on a power on reset (POR) event.
In order to achieve the lowest leakage current when both PECI and SB TSI are not used, set
the VREF_CPU Disable bit to 1.
The BC DAT pin requires a weak pull up resistor (100 K Ohms).
The voltage on the ADC pins must not exceed 3.6 V or damage to the device will occur.
The XTAL1 pin should be left floating when using the XTAL2 pin for the single ended clock
input.
The Boot ROM manipulates the pins associated with the Shared SPI interface and the Private
SPI interface to access the external flash. Before exiting, the Boot ROM tristates these inter-
faces by returning them to their default hardware state (i.e., GPIO input).
When the SMBxx_xxxx18 functions are selected, the pins operate at 1.8V I/O signal levels.
The GPIO assignment on this pin only provides interrupt and wakeup capability. This is pro-
vided by the Interrupt Detection field in the Pin Control register. The Mux control field in the Pin
Control Register should not be set to 00 = GPIO or undesirable results may occur. In order to
emphasize the prohibition on using the GPIO Signal Pin Function, the Pin Chapter does not list
the GPIO signal pin function assigned to this pin; however, the GPIO chapter does so the inter-
rupt can be used.
This signal is a test signal used to detect when the internal 48MHz clock is toggling or stopped
in heavy and deepest sleep modes.
The VCI pins may be used as GPIOs. The VCI input signals are not gated by selecting the
GPIO alternate function. Firmware must disable (i.e., gate) these inputs by writing the bits in
the VCI Input Enable Register when the GPIO function is enabled.
The KSI and KSO Key Scan pins require pull-up resistors. The system designer may opt to
use either use the internal pull-up resistors or populate external pull-up resistors.
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DS00001956D-page 13