MEC1404 Datasheet, PDF (423/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

31.11.2 BC-LINK ADDRESS REGISTER
MEC140X/1X
Offset ^04h
Bits
Description
31:8 Reserved
7:0 ADDRESS
Address in the Companion for the BC-Link transaction.
31.11.3 BC-LINK DATA REGISTER
Type
R
R/W
Default
-
0h
Reset
Event
-
nSYSR
ST
Offset ^08h
Bits
Description
Type
31:8 Reserved
R
7:0 DATA
R/W
As described in Section 31.10.1, "BC-Link Master READ Opera-
tion" and Section 31.10.2, "BC-Link Master WRITE Operation", this
register hold data used in a BC-Link transaction.
31.11.4 BC-LINK CLOCK SELECT REGISTER
Default
-
0h
Reset
Event
-
nSYSR
ST
Offset ^0Ch
Bits
Description
Type
31:8 Reserved
R
7:0 DIVIDER
R/W
The BC Clock is set to the Master Clock divided by this field, or
48MHz/ (Divider +1). The clock divider bits can only can be
changed when the BC Bus is in soft RESET (when either the Reset
bit is set by software or when the BUSY bit is set by the interface).
Settings for DIVIDER are shown in Table 31-5, "Frequency Set-
tings".
Default
-
4h
Reset
Event
-
nSYSR
ST
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DS00001956D-page 423