MEC1404 Datasheet, PDF (93/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^34h
Bits
Description
Type
5 VBAT reset status
Indicates the status of VBAT_POR.
0 = No reset occurred while VTR was off or since the last time this
bit was cleared.
1 = A reset occurred.
Note:
The bit will not clear if a write 1 is attempted at the same
time that a VBAT_RST_N occurs. This ensures a reset
event is never missed.
4 RESERVED
3 SIO_Reset Status
Indicates the status of nSIO_RESET.
0 = reset active.
1 = reset not active.
2 VCC_PWRGD Status
Indicates the status of VCC_PWRGD pin.
0 = VCC_PWRGD not asserted (Low).
1 = VCC_PWRGD asserted (High).
1:0 RESERVED
R/WC
RES
R
R
RES
Default
-
Reset
Event
nSYSR
ST
xh
Note 3-
3
xh
Note 3-
3
Note 3-3
This read-only status bit always reflects the current status of the event and is not affected by any
Reset events.
3.9.12 HOST RESET ENABLE REGISTER (HOST_RST_EN)
Offset ^3Ch
Bits
Description
31:19 RESERVED
18 RESERVED
17 RESERVED
16 8042EM Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
15 ACPI PM1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
14 ACPI EC 1 Reset Enable
0: block will not be reset on sleep.
1: block will be reset on sleep.
Type
RES
RES
RES
R/W
Default
Reset
Event
0h
nSYSR
ST
R/W
0h
nSYSR
ST
R/W
0h
nSYSR
ST
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DS00001956D-page 93