MEC1404 Datasheet, PDF (310/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 21-2: INTERNAL SIGNAL DESCRIPTION TABLE
Name
POWER_UP_EVENT
Direction
OUTPUT
Description
Signal to the VBAT-Powered Control Interface. When this signal is
asserted, the VCI output signal asserts. See Section 21.8, "Power-
Up Events".
21.4 Host Interface
The registers defined for the RTC/Week Timer are accessible only by the EC.
21.5 Power, Clocks and Resets
This section defines the Power, Clock, and Reset parameters of the block.
21.5.1 POWER DOMAINS
TABLE 21-3: POWER SOURCES
Name
VBAT
VTR
21.5.2 CLOCKS
Description
This power well sources all of the internal registers and logic in this block.
This power well sources only bus communication. The block continues to
operate internally while this rail is down.
TABLE 21-4: CLOCKS
Name
32KHz_Clk
21.5.3 RESETS
Description
This 32KHz clock input drives all internal logic, and will be present at all
times that the VBAT well is powered.
TABLE 21-5: RESET SIGNALS
Name
VBAT_POR
VTR_RESET#
Description
This reset signal is used reset all of the registers and logic in this block.
This reset signal is used to inhibit the bus communication logic, and iso-
lates this block from VTR powered circuitry on-chip. Otherwise it has no
effect on the internal state.
DS00001956D-page 310
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