MEC1404 Datasheet, PDF (243/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Note:
The IBF and OBF bits are not de-asserted by hardware when the host is powered off, or the LPC interface
powers down; for example, following system state changes S3->S0, S5->S0, G3-> S0. For further informa-
tion on how these bits are cleared, refer to IBF and OBF bit descriptions in the STATUS OS-Register defi-
nition.
14.13.10 EC BYTE CONTROL REGISTER
This register is aliased to the OS Byte Control Register on page 238. The OS Byte Control Register is a read only version
of this register.
Offset ^105h
Bits
Description
7:1 Reserved
0 FOUR_BYTE_ACCESS
See FOUR_BYTE_ACCESS bit in OS Byte Control Register on
page 238 for bit description.
Type
R
R/W
Default
-
0b
Reset
Event
-
nSYSR
ST
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DS00001956D-page 243