MEC1404 Datasheet, PDF (106/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
FIGURE 4-3:
CLOCK START ILLUSTRATION
SERIRQ MODE BIT
ANY CHANGE
CLKRUN#
LCLK
CLKRUN#
DRIVEN BY
MCHP Device
MCHP Device STOPS
DRIVING CLKRUN#
(after two rising edges of
LCLK)
2 CLKS MIN.
Note 1: The signal “ANY CHANGE” is the same as “CHANGE/ASSERTION” in TABLE 4-6:.
2: The LPC Controller must continually monitor the state of CLKRUN# to maintain LCLK until an active “any
IRQ change” condition has been transferred to the host in a Serial IRQ cycle or “any DRQ assertion” con-
dition has been transferred to the host in a DMA cycle. For example, if “any IRQ change or DRQ assertion”
is asserted before CLKRUN# is de-asserted (not shown in FIGURE 4-3:), the controller must assert
CLKRUN# as needed until the Serial IRQ cycle or DMA cycle has completed.
4.8.2 CLAIMING AND FORWARDING TRANSACTIONS FOR SUPPORTED LPC CYCLES
The following sections define how the LPC Controller determines if a cycle is targetted for one of the chip’s logical
devices and how that transaction is then forwarded to that logical device. The following sections include:
• Section 4.8.2.1, "I/O Transactions," on page 106
• Section 4.8.2.2, "Device Memory Transactions," on page 109
4.8.2.1 I/O Transactions
The system host will generate I/O commands to communicate with I/O peripherals, such as Keyboard Controller, UART,
etc. The LPC Controller will claim only I/O transactions targeted to it and it will ignore all others. The following sections
describe how I/O transactions are claimed and forwarded to access the Runtime and Configuration registers.
CLAIMING LPC I/O TRANSACTIONS
Each host I/O accessible block (i.e., logical device) has an associated I/O Base Address register. The format of this reg-
ister is defined in Section 4.9.3, "I/O Base Address Registers (IO_BARs)," on page 120. If the VALID bit is set in the
logical device’s BAR register the LPC interface will claim all I/O addresses that match the unmasked portion of the pro-
grammed LPC Host Address using the following equation.
(LPC Address & ~BAR.MASK) == (BAR.LPC_Address & ~BAR.MASK) && (BAR.Valid == 1)
Masked bits are treated as don’t care in the address matching decoder.
Note: The LPC Controller’s Base Address register is used to define the Base I/O Address of the Configuration
Port.
FORWARDING I/O TRANSACTIONS
Once an LPC Address is claimed for a specific logical device, the 8 LSbs of the I/O Address are used as the offset from
the hard-coded logical device’s Runtime Registers Base Address located in the EC/Host Address space (i.e., F_0000h
to F_FFFFh). This allows each Host I/O Accessible Block the ability to map up to 256 contiguous bytes into I/O space.
EC/Host Address = Logical Device Runtime Register Base Address[31:0] + (LPC I/O Address[6:0] & BAR.MASK)
Note: The Runtime Registers are always located on even 1k byte boundaries in the internal EC/Host Address
space.
DS00001956D-page 106
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