MEC1404 Datasheet, PDF (31/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

Interface
Signal Name
Quad SPI Master Controller SPI_IO2
Interface
Quad SPI Master Controller SPI_IO3
Interface
UART Port
CTS#
UART Port
DCD#
UART Port
DSR#
UART Port
DTR#
UART Port
RI#
UART Port
RTS#
UART Port
UART_CLK
UART Port
UART_RX
UART Port
UART_TX
VBAT-Powered Control
Interface
VBAT-Powered Control
Interface
VBAT-Powered Control
Interface
VBAT-Powered Control
Interface
VBAT-Powered Control
Interface
VBAT-Powered Control
Interface
BGPO
SYSPWR_PRES
VCI_IN0#
VCI_IN1#
VCI_OUT
VCI_OVRD_IN
MEC140X/1X
Description
Notes
General Purpose SPI Data 2
(SPI_IO2)
General Purpose SPI Data 3
(SPI_IO3)
Clear to Send Input
Data Carrier Detect Input
Data Set Ready Input
Data Terminal Ready Output
Ring Indicator Input
Request to Send Output
UART Baud Clock Input
UART Receive Data (RXD)
UART Transmit Data (TXD)
Battery Powered General
Purpose Output
Battery Powered System Power
Present Input
Input can cause wakeup or
interrupt event
Input can cause wakeup or
interrupt event
Output from combinatorial logic
and/or EC
Input can cause wakeup or
interrupt event
Note 12
Note 14
Note 14
Note 14
2.10 Pin Multiplexing
Multifunction Pin Multiplexing in the MEC140X/1X is controlled by the GPIO Interface and illustrated in the Pin Multi-
plexing Table in this section. See Section 2.3, "Notes for Tables in this Chapter," on page 13 for notes that are refer-
enced in the Pin Multiplexing Table. See Pin Control Register on page 335 for Pin Multiplexing programming details.
Pin signal functions that exhibit power domain emulation (see Pin Multiplexing Table below) have a different power sup-
ply designation in the “Emulated Power Well” column and “Signal Power Well“ columns.
2.10.1 VCC POWER DOMAIN EMULATION
The System Runtime Supply power VCC is not connected to the MEC140X/1X. The VCC_PWRGD signal is used to
indicate when power is applied to the System Runtime Supply.
Pin signal functions with VCC power domain emulation are documented in the Pin Multiplexing Table as “Signal Power
Well“= VTR and “Emulated Power Well” = VCC. These pins are powered by VTR and controlled by the VCC_PWRGD
signal input. Outputs on VCC power domain emulation pin signal functions are tri-stated when VCC_PWRGD is not
asserted and are functional when VCC_PWRGD is active. Inputs on VCC power domain emulation pin signal functions
are gated according as defined by the Gated State column in the following tables.
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DS00001956D-page 31