MEC1404 Datasheet, PDF (444/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Address ^00h
Bits
Description
4:1 Reserved
0 DET32K_IN
0 = No clock detected on the XTAL[1:2] pins.
1= Clock detected on the XTAL[1:2] pins.
Type
RES
R
Default
-
X
Reset
Event
-
VBAT_
POR
Note 35-2
In the MEC140X/1X devices the WDT defaults to disabled, however the Boot ROM Exception Handler
uses the WDT to generate a nSYSRST. The Boot ROM only touches the WDT if the BEV exception
fires. In this case 0x5 is written to the EC Subsystem WDT_COUNT bit field. The WDT Status bit,
located in the WDT EC-Only Register bank, and the WDT status bit located in the Power-Fail and
Reset Status Register register are cleared before the WDT is enabled.
35.7.2 CLOCK ENABLE REGISTER
Address ^08h
Bits
Description
31:6 Reserved
5 48MHz Oscillator Reference Select
0 = External 32KHz clock source is the 48MHz clock reference
(default)
1 = Switched Clock Source (i.e., either internal 32kHz or external
32kHz clock) is the 48MHz clock reference
Note:
The external 32KHz clock source may be either the crys-
tal or external single-ended 32kHz clock as selected by
the XOSEL bit.
4 32KHz Clock Switcher Control
This bit disables the clock switcher logic.
Type
RES
R/W
R/W
Default
-
0b
Reset
Event
-
VBAT_
POR
0b
VBAT_
(Note 35-3) POR
0 = If the device is configured to operate on the external single-
ended 32.768 KHz clock source and the clock switcher logic detects
that the external clock is turned off, it will automatically switch to the
internal 32k Hz clock source. It will remain operating on the internal
32k Hz clock source until it detects several good edges on the exter-
nal clock input. Once it determines the external clock is on, the clock
switcher will return control of the 32k Hz clock to the external pin.
Note:
Clock Switching only occurs when VTR is ON. The
behavior of the 32kHz clock when VTR is OFF is deter-
mined by the INT_32K VTR Power Well Emulation bit.
1 = clock switching is disabled. The device will only operate on the
clock enabled. See Table 35-3, "32kHz Clock Control" below.
3 INT_32K VTR Power Well Emulation
This bit determines the internal 32kHz clock behavior when VTR is
off.
0 = VBAT Emulation. The internal 32k Hz clock remains ON when
VTR is off.
1 = VTR Emulation. The internal 32k Hz clock is gated OFF when
VTR is off.
R/W
0b
VBAT_
(Note 35-3) POR
DS00001956D-page 444
 2015 - 2016 Microchip Technology Inc.