MEC1404 Datasheet, PDF (467/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^04h
Bits
Description
Type
31:16 Repeat_Delay[15:0]
R/W
This field determines the interval between conversion cycles when
Start_Repeat is 1. The delay is in units of 40s. A value of 0 means
no delay between conversion cycles, and a value of 0xFFFF
means a delay of 2.6 seconds.
This field has no effect when Start_Single is written with a 1.
Default
0000h
Reset
Event
nSYSR
ST
15:0 Start_Delay[15:0]
R/W
This field determines the starting delay before a conversion cycle is
begun when Start_Repeat is written with a 1. The delay is in units
of 40s. A value of 0 means no delay before the start of a conver-
sion cycle, and a value of 0xFFFF means a delay of 2.6 seconds.
This field has no effect when Start_Single is written with a 1.
0000h
nSYSR
ST
38.11.3 ADC STATUS REGISTER
The ADC Status Register indicates whether the ADC has completed a conversion cycle.
Offset ^08h
Bits
Description
Type
Default
Reset
Event
31:8 RESERVED
7:0 ADC_Ch_Status[7:0]
All bits are cleared by being written with a ‘1’.
0: conversion of the corresponding ADC channel is not complete
1: conversion of the corresponding ADC channel is complete
Note: for enabled single cycles, the Single_Done_Status bit in the
ADC Control Register is also set after all enabled channel conver-
sion are done; for enabled repeat cycles, the Repeat_Done_Status
in the ADC Control Register is also set after all enabled channel
conversion are done.
See Note 38-2.
RES
R/WC
00h
nSYSR
ST
Note 38-2 Bits that correspond to the unused channels are reserved. See Products on page 3 for the specific
number of channels supported for a particular device.
38.11.4 ADC SINGLE REGISTER
The ADC Single Register is used to control which ADC channel is captured during a Single-Sample conversion cycle
initiated by the Start_Single bit in the ADC Control Register.
APPLICATION NOTE: Do not change the bits in this register in the middle of a conversion cycle to insure proper
operation.
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DS00001956D-page 467