MEC1404 Datasheet, PDF (79/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 3-11: POWER, CLOCKS AND RESET VTR-POWERED REGISTERS SUMMARY
Offset
Register Name
34h
PCR chip sub-system power reset status (CHIP_P-
WR_RST_STS)
38h
Test Register
3Ch
Host Reset Enable Register (HOST_RST_EN)
40h
EC Reset Enable Register (EC_RST_EN)
44h
EC Reset Enable 2 Register (EC_RST_EN2)
48h
Power Reset Control (PWR_RST_CTRL) Register
Note: All register addresses are naturally aligned on 32-bit boundaries. Offsets for registers that are smaller than
32 bits are reserved and must not be used for any other purpose.
3.9 Sleep Enable and Clock Required Registers
The following are the Sleep Enable and Clock Required registers for the MEC140X/1X.
3.9.1 EC SLEEP ENABLE REGISTER (EC_SLP_EN)
Offset ^08h
Bits
Description
31 TIMER16_1 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note: on page 81.
30 TIMER16_0 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
See Note: on page 81.
29 EC_REG_BANK Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
28:27 RESERVED
26 PWM7 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
25 PWM6 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
24 PWM5 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
23 PWM4 Sleep Enable
0: block is free to use clocks as necessary.
1: block is commanded to sleep at next available moment.
Type
R/W
Default
0h
Reset
Event
nSYSR
ST
R/W
0h
nSYSR
ST
R/W
RES
R/W
R/W
R/W
R/W
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
0h
nSYSR
ST
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