MEC1404 Datasheet, PDF (274/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
TABLE 17-1: SIGNAL DESCRIPTION TABLE (CONTINUED)
Name
DCD#
DSR#
RI#
RTS#
CTS#
TXD
RXD
UART_CLK
Direction
Output
Input
Input
Output
Input
Output
Input
Input
Description
Active low Data Carrier Detect input for the serial port.
Handshake signal which notifies the UART that carrier signal is
detected by the modem. The CPU can monitor the status of DCD#
signal by reading bit 7 of Modem Status Register (MSR). A DCD#
signal state change from low to high after the last MSR read will
set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the
interrupt is generated when DCD # changes state.
Active low Data Set Ready input for the serial port. Handshake
signal which notifies the UART that the modem is ready to estab-
lish the communication link. The CPU can monitor the status of
DSR# signal by reading bit 5 of Modem Status Register (MSR). A
DSR# signal state change from low to high after the last MSR read
will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when DSR# changes state.
Active low Ring Indicator input for the serial port. Handshake sig-
nal which notifies the UART that the telephone ring signal is
detected by the modem. The CPU can monitor the status of RI#
signal by reading bit 6 of Modem Status Register (MSR). A RI#
signal state change from low to high after the last MSR read will
set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the
interrupt is generated when nRI changes state.
Active low Request to Send output for the Serial Port. Handshake
output signal notifies modem that the UART is ready to transmit
data. This signal can be programmed by writing to bit 1 of the
Modem Control Register (MCR). The hardware reset will reset the
RTS# signal to inactive mode (high). RTS# is forced inactive
during loop mode operation. Defaults to tri-state on V3_DUAL
power on.
Active low Clear to Send input for the serial port. Handshake sig-
nal which notifies the UART that the modem is ready to receive
data. The CPU can monitor the status of CTS# signal by reading
bit 4 of Modem Status Register (MSR). A CTS# signal state
change from low to high after the last MSR read will set MSR bit 0
to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is
generated when CTS# changes state. The CTS# signal has no
effect on the transmitter.
Transmit serial data output.
Receiver serial data input.
External Baud Clock Generator input. The source of the baud
clock is controlled by CLK_SRC on page 278.
17.5 Host Interface
The UART is accessed by host software via a registered interface, as defined in Section 17.10, "Configuration Regis-
ters"and Section 17.11, "Runtime Registers".
DS00001956D-page 274
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