MEC1404 Datasheet, PDF (468/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
Offset ^0Ch
Bits
Description
Type
31:8 RESERVED
7:0 Single_En[7:0]
0: single cycle conversions for this channel are disabled
1: single cycle conversions for this channel are enabled
Each bit in this field enables the corresponding ADC channel when
a single cycle of conversions is started when the Start_Single bit in
the ADC Control Register is written with a 1.
See Note 38-2.
RES
R/W
Default
Reset
Event
00h
nSYSR
ST
38.11.5 ADC REPEAT REGISTER
The ADC Repeat Register is used to control which ADC channels are captured during a repeat conversion cycle initiated
by the Start_Repeat bit in the ADC Control Register.
Offset ^10h
Bits
Description
31:8
RESERVED
7:0
Rpt_En[7:0]
0: repeat conversions for this channel are disabled
1: repeat conversions for this channel are enabled
Each bit in this field enables the corresponding ADC channel for
each pass of the Repeated ADC Conversion that is controlled by
bit Start_Repeat in the ADC Control Register.
See Note 38-2.
Type
RES
R/W
Default
Reset
Event
00h
nSYSR
ST
38.11.6 ADC CHANNEL READING REGISTERS
All 8 ADC channels return their results into a 32-bit reading register. In each case the low 10 bits of the reading register
return the result of the Analog to Digital conversion and the upper 22 bits return 0. Table 38-3, “Analog to Digital Con-
verter Register Summary,” on page 464 shows the addresses of all the reading registers.
Note 38-3 The ADC Channel Reading Registers access require single 16, or 32 bit reads; i.e., two 8 bit reads
cannot ensure data coherency.
DS00001956D-page 468
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