MEC1404 Datasheet, PDF (148/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
6.11.9 QMSPI TRANSMIT BUFFER REGISTER
Offset ^20h
Bits
Description
Type
31:0 TRANSMIT_BUFFER
W
Writes to this register store data to be transmitted from the SPI
Master to the external SPI Slave. Writes to this block will be written
to the Transmit FIFO. A 1 Byte write fills 1 byte of the FIFO. A Word
write fills 2 Bytes and a Doubleword write fills 4 bytes. The data
must always be aligned to the bottom most byte (so 1 byte write is
on bits [7:0] and Word write is on [15:0]). An overflow condi-
tion,TRANSMIT_BUFFER_ERROR, if a write to a full FIFO occurs.
Write accesses to this register increment the TRANS-
MIT_BUFFER_COUNT field.
6.11.10 QMSPI RECEIVE BUFFER REGISTER
Default
0h
Reset
Event
RESET
Offset ^24h
Bits
Description
Type
31:0 RECEIVE_BUFFER
R
Buffer that stores data from the external SPI Slave device to the
SPI Master (this block), which is received over MISO or IO.
Reads from this register will empty the Rx FIFO. A 1 Byte read will
have valid data on bits [7:0] and a Word read will have data on bits
[15:0]. It is possible to request more data than the FIFO has
(underflow condition), but this will cause an error (Rx Buffer Error).
Read accesses to this register decrement the
RECEIVE_BUFFER_COUNT field.
Default
0h
Reset
Event
RESET
DS00001956D-page 148
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