MEC1404 Datasheet, PDF (98/572 Pages) Microchip Technology – Keyboard and Embedded Controller Products for Notebook PC

MEC140X/1X
3.9.15 POWER RESET CONTROL (PWR_RST_CTRL) REGISTER
Offset ^48h
Bits
Description
Type
31:2 RESERVED
1 Host_Reset_Select
This bit determines the platform reset signal that will be used to
assert nSIO_RESET. See FIGURE 3-2: Resets Diagram
(MEC140x/1X) on page 74.
0 = LRESET# pin generates internal Platform Reset
1 = eSPI Platform Reset (eSPI_PLTRST#)
0 iRESET_OUT
The iRESET_OUT bit is used by firmware to control the internal
nSIO_RESET signal function and the external nRESET_OUT pin.
The external pin nRESET_OUT is always driven by nSIO_RESET.
Firmware can program the state of iRESET_OUT except when the
VCC_PWRGD pin is not asserted (‘0’), in which case iRE-
SET_OUT is ‘don’t care’ and nSIO_RESET is asserted (‘0’)
(TABLE 3-13:).
The internal nSIO_RESET signal is asserted when iRESET_OUT
is asserted even if the nRESET_OUT pin is configured as an alter-
nate function.
The iRESET_OUT bit must be cleared to take the Host accessible
peripherals out of reset. See Section 1.5, "MEC140x Internal
Address Spaces," on page 10 for host accessible peripherals.
RES
R/W
R/W
Default
Reset
Event
0h
nSYSR
ST
1h
nSYSR
ST
TABLE 3-13: iRESET_OUT BIT BEHAVIOR
nSYSRST
0
1
VCC_PWRGD
X
0
1
PCI_RESET#
X
X
0
1
iRESET_OUT
X
X
X
1
0
nSIO_RESET & nRESET_OUT
0 (ASSERTED)
0 (ASSERTED)
0 (ASSERTED)
0 (ASSERTED)
1 (NOT ASSERTED)
DS00001956D-page 98
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