HD6417727BP160CV Datasheet, PDF (998/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 32 Electrical Characteristics
Table 32.8 Clock Timing (4)
Conditions: VccQ = 3.0 to 3.6 V, Vcc = 1.75 to 2.05 V, AVcc = 3.3 ± 0.3 V, Ta = –20 to 75°C,
160 MHz products
Item
Symbol Min
Max
Unit
Figure
EXTAL clock input frequency
f_EX
6
EXTAL clock input cycle time
t_EXcyc
15
EXTAL clock input low pulse width
t_EXL
1.5
EXTAL clock input high pulse width
t_EXH
1.5
EXTAL clock input rise time
t_EXR
—
EXTAL clock input fall time
t_EXF
—
CKIO clock input frequency
f_CKI
24
CKIO clock input cycle time
t_CKIcyc
15
CKIO clock input low pulse width
t_CKIL
1.5
CKIO clock input high pulse width
t_CKIH
1.5
CKIO clock input rise time
t_CKIR
—
CKIO clock input fall time
t_CKIF
—
CKIO clock output frequency
f_OP
24
CKIO clock output cycle time
t_cyc
15
CKIO clock output low pulse width
t_CKOL
3
CKIO clock output high pulse width
t_CKOH
3
CKIO clock output rise time
t_CKOR
—
CKIO clock output fall time
t_CKOF
—
CKIO2 clock output delay time
t_CK2D
—
CKIO2 clock output rise time
t_CK2OR
—
CKIO2 clock output fall time
t_CK2OF
—
Power-on oscillation settling time
RESETP setup time
(At power on and cancellation of standby mode)
t_OSC1
10
t_RESPS
20
RESETM setup time (At cancellation of standby mode) t_RESMS
0
RESETP assert time
(At power on and cancellation of standby mode)
t_RESPW
20
RESETM assert time (At cancellation of standby mode) t_RESMW
20
Standby return oscillation settling time 1
t_OSC2
10
Standby return oscillation settling time 2
t_OSC3
10
Standby return oscillation settling time 3
t_OSC4
11
PLL synchronization settling time 1 (At cancellation of
t_PLL1
100
standby mode)
66.67
166.7
—
—
6
6
66.67
41.7
—
—
6
6
66.67
41.7
—
—
5
5
2.5
7
7
—
—
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
—
ns
—
t_cyc
—
t_cyc
—
ms
—
ms
—
ms
—
μs
32.3
32.4
32.5
32.6
32.6, 32.7
32.7
32.8
32.9
32.10,
32.11
PLL synchronization settling time 2 (At multiplier change) t_PLL2
100
—
μs
32.12
IRQ/IRL interrupt determination time
(RTC used and standby mode)
t_IRQSTB
100
—
μs
32.11
Rev.6.00 Mar. 27, 2009 Page 940 of 1036
REJ09B0254-0600