HD6417727BP160CV Datasheet, PDF (113/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
Table 2.14 CPU Instruction Formats
Instruction Format
Source
Operand
Destination
Operand
Sample Instruction
0 type
—
—
NOP
15
0
xxxx xxxx xxxx xxxx
n type
15
xxxx nnnn xxxx
m type
15
xxxx mmmm xxxx
0
xxxx
0
xxxx
—
nnnn: register MOVT Rn
direct
Control register or nnnn: register
system register direct
STS MACH,Rn
Control register or nnnn: pre-
STC.L SR,@-Rn
system register decrement register
indirect
mmmm: register
direct
Control register or LDC Rm,SR
system register
mmmm: post-
Control register or LDC.L @Rm+,SR
increment register system register
indirect
mmmm: register —
indirect
JMP @Rm
PC-relative using —
Rm
BRAF Rm
Rev.6.00 Mar. 27, 2009 Page 55 of 1036
REJ09B0254-0600