HD6417727BP160CV Datasheet, PDF (697/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
20.3.6 FIFO
(1) Outline
Features of SIOF transmit or receive FIFO are listed as below.
• Capacity of 32 bits × 16 stages for each of transmission and reception
• Pointer is updated by a read/write cycle for all of the access sizes of CPU and DMAC
(It is impossible to separate one stage access to multiple times)
• Access cycle number is always 2 cycles (P bus cycle) for all of the access sizes.
(2) Transmit Request
Transmit request of FIFO is displayed in the following two bits of SISTR register.
• Transmit request: TDREQ (transmit interrupt factor)
• Receive request: RDREQ (receive interrupt factor)
It is possible to set independently the condition for each of submitting transmit request of transmit
or receive FIFO. Condition of transmit request are set to bits TFWM2 to TFWM0 in SIFCTR
register and transfer request of receive FIFO are set to bits RFWM2 to RFWM0.
Table 20.9 shows transmit request submit condition, and table 20.10 shows receive request submit
condition.
Table 20.9 Transmit Request Submit Condition
TFWM2 to TFWM0
000
100
101
110
111
Request Stage
Number
1
4
8
12
16
Transmit Request Submit
16 stages empty area
Over 12 stages empty area
Over 8 stages empty area
Over 4 stages empty area
Over 1 stage empty area
Used Area
Small
Large
Rev.6.00 Mar. 27, 2009 Page 639 of 1036
REJ09B0254-0600