HD6417727BP160CV Datasheet, PDF (167/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 3 Memory Management Unit (MMU)
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry
are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not
when there is sharing (SH = 1).
When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged
(SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared
when single virtual memory is supported and privileged mode is engaged. The objects of address
comparison are shown in figure 3.8.
SH = 1 or
(SR.MD = 1 and
No
MMUCR.SV = 1)?
Yes
SZ = 0?
No (4 kbytes)
SZ = 0?
No (4 kbytes)
Yes (1 kbyte)
Yes (1 kbyte)
Bits compared:
VPN (31−17)
VPN (11−10)
Bits compared:
VPN (31−17)
Bits compared:
VPN (31−17)
VPN (11−10)
ASID (7−0)
Bits compared:
VPN (31−17)
ASID (7−0)
Figure 3.8 Objects of Address Comparison
Rev.6.00 Mar. 27, 2009 Page 109 of 1036
REJ09B0254-0600