HD6417727BP160CV Datasheet, PDF (395/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data
including the missed data is read in wraparound mode.
CKIO,
CKIO2
A25 to A16,
A13
Tr Trw Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 Tpc
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
Figure 12.14 Synchronous DRAM Burst Read Wait Specification Timing
Single Read: Figure 12.15 shows the timing when a single address read is performed. As the burst
length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is
output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is
accessed.
Rev.6.00 Mar. 27, 2009 Page 337 of 1036
REJ09B0254-0600