HD6417727BP160CV Datasheet, PDF (206/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby
mode, however, the interrupt will be accepted even when the BL bit in SR is 1.
NMI is accepted when BLMSK in ICR1 is 1, regardless of the setting of the BL bit.
⎯ Exception: No user break point trap will occur even when the break conditions are met.
When one of the other exceptions occurs, a branch is made to the fixed address of the reset
(H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are
undefined.
• SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as
shown below:
⎯ Re-executing-type exceptions: The PC of the instruction that caused the exception is set in
the SPC and re-executed after return from exception handling. If the exception occurred in
a delay slot, however, the PC of the immediately prior delayed branch instruction is set in
the SPC. If the condition of the conditional delayed branch instruction is not satisfied, the
delay slot PC is set in SPC.
⎯ Completed-type exceptions and interrupts: The PC of the instruction after the one that
caused the exception is set in the SPC. If the exception was caused by a delayed
conditional branch instruction, however, the branch destination PC is set in SPC. If the
condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is
set in SPC.
• Initial register values after reset
⎯ Undefined registers
R0_BANK0/1 to R7_BANK0/1, R8 to R15, GBR, SPC, SSR, MACH, MACL, PR
⎯ Initialized registers
VBR = H'00000000
SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3 to SR.I0 = H'F. Other SR bits are undefined.
PC = H'A0000000
• Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not
guaranteed in this case.
• When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address
error does not occur at an LDC instruction that updates the SR register and the following
instruction. This occurrence will be identified as multiple exceptions, and may initiate reset
processing.
Rev.6.00 Mar. 27, 2009 Page 148 of 1036
REJ09B0254-0600