HD6417727BP160CV Datasheet, PDF (198/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 4 Exception Handling
6. Instruction execution jumps to the vector location designated by the sum of the value of the
contents of the vector base register (VBR) and H'00000600 to invoke the exception handler.
4.4.3 General Exceptions
When the SH7727 encounters any exception condition other than a reset or interrupt request, it
executes the following operations:
1. The contents of the PC and SR are saved in the SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except NMI interrupt when
BLMSK bit is 1).
3. The MD bit in SR is set to 1 to place the SH7727 in privileged mode.
4. The RB bit in SR is set to 1.
5. An encoded value identifying the exception event is written to bits 11 to 0 of the EXPEVT
register.
6. Instruction execution jumps to the vector location designated by either the sum of the vector
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
4.5 Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations.
4.5.1 Resets
• Power-On Reset
⎯ Conditions: RESETP low
⎯ Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'00000000. In SR, the MD, RB and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) is set to 1111. The CPU and on-chip supporting
modules are initialized. See the register descriptions in the relevant sections for details. A
power-on reset must always be performed when powering on. A high level is output from
the STATUS0 and STATUS1 pins.
Rev.6.00 Mar. 27, 2009 Page 140 of 1036
REJ09B0254-0600