HD6417727BP160CV Datasheet, PDF (363/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
For Synchronous DRAM Interface: (see table 12.12)
Bit6: Bit5: Bit 4: Bit 3:
AMX3 AMX2 AMX1 AMX0 Description
1
1
0
1
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 4M × 16-bit × 4-bank products)
1
0
The row address begins with A11 when bus width is 16 bit.
(The A11 value is output at A1 when the row address is
output. 8M × 16-bit × 4-bank products)^*1
0
1
0
0
The row address begins with A9 when bus width is 16 bit.
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 1M × 16-bit × 4-bank products)
1
The row address begins with A10 when bus width is 16 bit.
The row address begins with A11 when bus width is 32 bit.
(The A10 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
1
0
The row address begins with A11 when bus width is 32 bit.^*2
(The A11 value is output at A1 when the row address is
output. 2M × 16-bit × 4-bank products)
1
The row address begins with A9 when bus width is 16 bit.
The row address begins with A10 when bus width is 32 bit.
(The A9 value is output at A1 when the row address is
output. 512K × 32-bit × 4-bank products)
0
0
0
Reserved. AMX3 to AMX0 must be set to *1*** before
accessing synchronous DRAM memory.
(Initial value)
Values other than above
Reserved (illegal setting)
Notes: 1. Can only be set when using a 16-bit bus width.
2. Can only be set when using a 32-bit bus width.
Rev.6.00 Mar. 27, 2009 Page 305 of 1036
REJ09B0254-0600