HD6417727BP160CV Datasheet, PDF (22/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

7.2.2 IRQ Interrupt........................................................................................................ 169
7.2.3 IRL Interrupts ...................................................................................................... 170
7.2.4 PINT Interrupt...................................................................................................... 172
7.2.5 On-Chip Supporting Module Interrupts ............................................................... 172
7.2.6 Interrupt Exception Handling and Priority........................................................... 173
7.3 INTC Registers ................................................................................................................. 179
7.3.1 Interrupt Priority Registers A to G (IPRA to IPRG) ............................................ 179
7.3.2 Interrupt Control Register 0 (ICR0)..................................................................... 180
7.3.3 Interrupt Control Register 1 (ICR1)..................................................................... 181
7.3.4 Interrupt Control Register 2 (ICR2)..................................................................... 184
7.3.5 Interrupt Control Register 3 (ICR3)..................................................................... 185
7.3.6 PINT Interrupt Enable Register (PINTER).......................................................... 187
7.3.7 Interrupt Request Register 0 (IRR0) .................................................................... 187
7.3.8 Interrupt Request Register 1 (IRR1) .................................................................... 190
7.3.9 Interrupt Request Register 2 (IRR2) .................................................................... 191
7.3.10 Interrupt Request Register 3 (IRR3) .................................................................... 192
7.3.11 Interrupt Request Register 4 (IRR4) .................................................................... 195
7.4 INTC Operation ................................................................................................................ 197
7.4.1 Interrupt Sequence ............................................................................................... 197
7.4.2 Multiple Interrupts ............................................................................................... 199
7.5 Interrupt Response Time ................................................................................................... 199
Section 8 User Break Controller ..................................................................................... 203
8.1 Overview........................................................................................................................... 203
8.1.1 Features................................................................................................................ 203
8.1.2 Block Diagram..................................................................................................... 204
8.1.3 Register Configuration......................................................................................... 205
8.2 Register Descriptions ........................................................................................................ 206
8.2.1 Break Address Register A (BARA) ..................................................................... 206
8.2.2 Break Address Mask Register A (BAMRA)........................................................ 206
8.2.3 Break Bus Cycle Register A (BBRA).................................................................. 207
8.2.4 Break Address Register B (BARB)...................................................................... 209
8.2.5 Break Address Mask Register B (BAMRB) ........................................................ 210
8.2.6 Break Data Register B (BDRB) ........................................................................... 211
8.2.7 Break Data Mask Register B (BDMRB).............................................................. 212
8.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 213
8.2.9 Break Control Register (BRCR) .......................................................................... 215
8.2.10 Execution Times Break Register (BETR)............................................................ 218
8.2.11 Branch Source Register (BRSR).......................................................................... 219
8.2.12 Branch Destination Register (BRDR).................................................................. 220
8.2.13 Break ASID Register A (BASRA)....................................................................... 221
Rev.6.00 Mar. 27, 2009 Page xx of lvi
REJ09B0254-0600