HD6417727BP160CV Datasheet, PDF (126/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Instruction
Instruction Code
Operation
Privilege
Execution
States T Bit
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
OP: Operation code
Sz: Size
SRC: Source
DEST: Destination
Indicated in MSB ↔
LSB order.
Indicates summary of
operation.
Indicates a
privileged
instruction.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
0000: R0
0001: R1
.........
Explanation of Symbols
→, ←: Transfer direction
(xx): Memory operand
M/Q/T: Flag bits in the SR
&: Logical AND of each bit
Value
Value of T
when no bit after
wait states instruction
are
is executed.
inserted.^*1 _Explanation
of Symbols
—: No
change
Rm: Source register
1111: R15
|: Logical OR of each bit
Rn: Destination register
imm: Immediate data
disp: Displacement
iiii: Immediate data
dddd: Displacement^*2
^: Exclusive logical OR of
each bit
~: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
(1) When there is contention between an instruction fetch and a data access
(2) When the destination register of a load instruction (memory → register) is also used
by the following instruction
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
Rev.6.00 Mar. 27, 2009 Page 68 of 1036
REJ09B0254-0600