HD6417727BP160CV Datasheet, PDF (798/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 24 USB HOST Module
Register: HcInterruptDisable
Bits
Reset R/W
0
0b
R/W
Offset: 14–17
Description
SchedulingOverrunEnable (SO)
0: Ignore
1: Disable interrupt generation due to Scheduling Overrun.
24.2.7 HcHCCA
HCCA Register (H'04000418)
The HcHCCA register includes physical addresses of the host controller communication area. The
host controller driver determines the alignment limitation by writing 1 to all bits in the HcHCCA
register and by reading the content of the HcHCCA register. Alignment is evaluated by checking
the number of 0 in the lower bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7
must be always returned to 0 when they are read. This area is used to retain the control structure
and interrupt table that are accessed by the host controller and host controller driver.
Register: HcHCCA
Bits
Reset R/W
31–8
0h
R/W
7–0
0h
—
Offset: 18–1B
Description
HCCA
Reserved.
24.2.8 HcPeriodCurrentED
HcPeriodCurrentED Register (H'0400041C)
The HcPeriodCurrentED register includes a physical address of current Isochronous ED or
Interrupt ED.
Register: HcPeriodCurrentED
Bits
Reset R/W
31–4
0h
R/W
3–0
0h
—
Offset: 1C–1F
Description
PeriodCurrentED (PCED)
Pointer to the current Periodic List ED. (Within memory area3)
Reserved.
Rev.6.00 Mar. 27, 2009 Page 740 of 1036
REJ09B0254-0600