HD6417727BP160CV Datasheet, PDF (544/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
17.1.4 Register Configuration
Table 17.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clock synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Table 17.2 Registers
Name
Abbreviation R/W Initial Value Address
Access size
Serial mode register SCSMR
R/W H'00
H'FFFFFE80 8
Bit rate register
SCBRR
R/W H'FF
H'FFFFFE82 8
Serial control register SCSCR
R/W H'00
H'FFFFFE84 8
Transmit data register
Serial status register
SCTDR
SCSSR
R/W H'FF
R/(W)^*1 H'84
H'FFFFFE86 8
H'FFFFFE88 8
Receive data register SCRDR
R
H'00
H'FFFFFE8A 8
Port SC data register SCPDR
R/W H'00
H'04000136 8
(H'A4000136)^*2
Port SC control register SCPCR
R/W H'8008
H'04000116 16
(H'A4000116)^*2
Notes: Registers with addresses beginning at H'04 are located in area 1 of physical space.
Consequently, when the cache is on, either access these registers from the P2 area of
logical space or else make an appropriate setting using the MMU so that these registers
are not cached.
1. The only value that can be written is 0 to clear the flags.
2. When address translation by the MMU is not executed, the address in parentheses
should be used.
Rev.6.00 Mar. 27, 2009 Page 486 of 1036
REJ09B0254-0600