HD6417727BP160CV Datasheet, PDF (489/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 14 Direct Memory Access Controller (DMAC)
14.4 Compare-Match Timer (CMT)
14.4.1 Overview
The DMAC has an on-chip compare-match timer (CMT) to generate DMA transfer requests. The
CMT is 16-bit counter.
Features
The CMT has the following features:
• Four types of counter input clocks can be selected
⎯ One of four internal clocks (Pφ/4, Pφ/8, Pφ/16, and Pφ/64) can be selected.
• Generates a DMA transfer request when a compare-match occurs.
Block Diagram
Figure 14.26 shows a CMT block diagram.
Pφ/4 Pφ/8 Pφ/16 Pφ/64
Control circuit
Clock selection
CMT
Module bus
Bus
interface
CMSTR: Compare match timer start register
CMCSR0: Compare match timer control/status register 0
CMCOR0: Compare match timer constant register 0
CMCNT0: Compare match timer counter 0
Internal bus
Figure 14.26 CMT Block Diagram
Rev.6.00 Mar. 27, 2009 Page 431 of 1036
REJ09B0254-0600