HD6417727BP160CV Datasheet, PDF (801/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 24 USB HOST Module
24.2.14 HcFmInterval
HcFmInterval Register (H'04000434)
The HcFmInterval register includes a 14-bit value indicating the bit time interval of the frame (i.e.,
between two serial SOFs) and a 15-bit value indicating the maximum packet size at a full speed
that is transmitted and received by the host controller without causing scheduling overrun. The
host controller driver adjusts the frame interval minutely by writing a new value over the current
value in each SOF. This supplies required programming ability to the host controller to
synchronize with an external clock source and to synchronize with offset of an unknown local
clock.
Register: HcFmInterval
Bits
Reset R/W
31
0b
R/W
30–16 0h
R/W
15–14
13–0
0h
—
2EDFh R/W
Offset: 34–37
Description
FrameIntervalToggle (FIT)
This bit is toggled by HCD whenever it loads a new value into
FrameInterval.
FSLargestDataPacket (FSMPS)
This field specifies a value which is loaded into the Largest Data
Packet Counter at the beginning of each frame.
The counter value expresses the largest data amount of the bit
that can be transmitted and received in one transaction by the
host controller at any given time without causing scheduling
overrun. The field value is calculated by HCD.
Reserved.
FrameInterval (FI)
These bits specifies the interval between two serial SOFs with
bit times. The nominal value is set to 11999. HCD must store
the current value of this field before resetting the host controller.
With this procedure, this bit is reset to its nominal value by the
host controller by setting the HostControllerReset bit in the
HcCommandStatus register. HCD can select to restore the
stored value at the completion of the reset sequence.
Rev.6.00 Mar. 27, 2009 Page 743 of 1036
REJ09B0254-0600