HD6417727BP160CV Datasheet, PDF (118/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
Table 2.16 Single Data Transfer Instruction Formats
Type
Mnemonic
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Single MOVS.W @-As,Ds 1 1 1 1 0 1 As Ds 0:(*)
0000
data
MOVS.W @As,Ds
0:R4
1:(*)
01
transfer MOVS.W @As+,Ds
1:R5
2:(*)
10
MOVS.W @As+Is,Ds
2:R2
3:(*)
11
MOVS.W Ds,@-As
3:R3
4:(*)
0001
MOVS.W Ds,@As
5:A1
01
MOVS.W Ds,@As+
6:(*)
10
MOVS.W Ds,@As+Is
7:A0
11
MOVS.L @-As,Ds
8:X0
0010
MOVS.L @As,Ds
9:X1
01
MOVS.L @As+,Ds
A:Y0
10
MOVS.L @As+Is,Ds
B:Y1
11
MOVS.L Ds,@-As
C:M0
0011
MOVS.L Ds,@As
D:A1G 0 1
MOVS.L Ds,@As+
E:M1
10
MOVS.L Ds,@As+Is
F:A0G 1 1
Note: * Codes reserved for system use.
Parallel Processing Instructions: Parallel processing instructions are provided for efficient
execution of digital signal processing using the DSP unit. They are 32 bits long and allow four
simultaneous processes, an ALU operation, multiplication, and two data transfers.
Parallel processing instructions are divided into an A field and a B field. The A field defines data
transfer instructions and the B field an ALU operation instruction and multiply instruction. These
instructions can be defined independently, and the processing is executed in parallel,
independently and simultaneously. A-field parallel data transfer instructions are shown in table
2.17, and B-field ALU operation instructions and multiply instructions in table 2.18.
Rev.6.00 Mar. 27, 2009 Page 60 of 1036
REJ09B0254-0600