HD6417727BP160CV Datasheet, PDF (111/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
DSP Addressing Operations: DSP addressing operations in the pipeline execution stage (EX),
including modulo addressing, are shown below.
if ( Operation is MOVX.W MOVY.W ) {
ABx=Ax; ABy=Ay;
/* memory access cycle uses ABx and ABy. The addresses to be used
have not been updated */
/* Ax is one of R4,R5 */
if ( DMX==0 || DMX==1 && DMY == 1 )} Ax=Ax+(+2 or R8[Ix] or +0);
/* Inc,Index,Not-Update */
else if (! not-update) Ax=modulo( Ax, (+2 or R8[Ix]) );
/* Ay is one of R6,R7 */
if ( DMY==0 ) Ay=Ay+(+2 or R9[Iy] or +0); /* Inc,Index,Not-Update */
else if (! not-update) Ay=modulo( Ay, (+2 or R9[Iy]) );
}
else if ( Operation is MOVS.W or MOVS.L ) {
if ( Addressing is Nop, Inc, Add-index-reg ) {
MAB=As;
/* memory access cycle uses MAB. The address to be used has not
been updated */
/* As is one of R2 to R5 */
As=As+(+2 or +4 or R8[Is] or +0); /* Inc,Index,Not-Update */
else { /* Decrement, Pre-update */
/* As is one of R2 to R5 */
As=As+(-2 or -4);
MAB=As;
/* memory access cycle uses MAB. The address to be used has been
updated */
}
Rev.6.00 Mar. 27, 2009 Page 53 of 1036
REJ09B0254-0600