HD6417727BP160CV Datasheet, PDF (163/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 3 Memory Management Unit (MMU)
3.3 TLB Functions
3.3.1 Configuration of the TLB
The TLB caches address translation table information located in the external memory. The address
translation table stores the physical page number translated from the virtual page number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 3.4 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 3.5 shows the configuration of logical
addresses and TLB entries.
Ways 0 to 3
Ways 0 to 3
Entry 0
Entry 1
VPN(31−17) VPN(11−10) ASID(7−0) V
Entry 0 PPN(31−10) PR(1−0) SZ C D SH
Entry 1
Entry 31
Address array
Entry 31
Data array
Figure 3.4 Overall Configuration of the TLB
Rev.6.00 Mar. 27, 2009 Page 105 of 1036
REJ09B0254-0600