HD6417727BP160CV Datasheet, PDF (366/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Bits 11, 7, and 6—Area 5 Address OE/WE Assert Delay (A5TED2, A5TED1, and A5TED0):
The A5TED bits specify the address to OE/WE assert delay time for the PCMCIA interface
connected to area 5.
Bit 11:
A5TED2
0
1
Bit 7:
A5TED1
0
1
0
1
Bit 6:
A5TED0
0
1
0
1
0
1
0
1
Description
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
Bits 10, 5 and 4—Area 6 Address OE/WE Assert Delay (A6TED2, A6TED1, and A6TED0):
The A6TED bits specify the address to OE/WE assert delay time for the PCMCIA interface
connected to area 6.
Bit 10:
A6TED2
0
1
Bit 5:
A6TED1
0
1
0
1
Bit 4:
A6TED0
0
1
0
1
0
1
0
1
Description
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 308 of 1036
REJ09B0254-0600