HD6417727BP160CV Datasheet, PDF (405/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
12.3.5 Burst ROM Interface
Setting bits A0BST (1, 0), A5BST (1, 0), and A6BST (1, 0) in BCR1 to a non-zero value allows
burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides high-speed
access to ROM that has a nibble access function. The timing for nibble access to burst ROM is
shown in figure 12.22. Two wait cycles are set. Basically, access is performed in the same way as
for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address
is changed before the next access is executed. When 8-bit ROM is connected, the number of
consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1, 0), A5BST (1, 0), or A6BST (1,
0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is
connected, only 4 can be set.
WAIT pin sampling is performed in the first access if one or more wait states are set, and is
always performed in the second and subsequent accesses.
Even if no wait state insertion is specified in burst ROM interface settings, two wait cycles are
automatically inserted in the second and subsequent accesses as shown in figure 12.23.
However, the WAIT signal is ignored in the following three cases:
• When writing to an external address area using DMA 16-byte transfer in dual address mode
• When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in single address mode
• During cache write-back access
Rev.6.00 Mar. 27, 2009 Page 347 of 1036
REJ09B0254-0600