HD6417727BP160CV Datasheet, PDF (700/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
(2) Receiving in Master
Figure 20.10 shows an example of receiving and operation in master.
No.
Time chart
Start
Settting of SIMDR register,
1 _{SISCR register, SITDAR register,}
SIRDAR register, SICDAR register,
SIFCTR register
2 "1" is set to SCKE bit of SICTR register
Setting content of SIOF
Setting of operation mode,
serial clock, slot position of
transmit or receive data,
slot position of control data
and limit of FIFO request
Set the beggin to operation
of baud rate generator
SIOF operation
3 SCK_SIO begin to transmit
Transmit serial clock
4 “1” is set to FSE bit of SICTR register
Set the begin to transmit of Transmit frame
frame synchronized signal synchronized signal
5 "1" is set to RXE bit of SICTR register
6
Synchronized to SIOFSYNC receive data
from RxD_SIO is stored to SIRDR
Set the transmit enable
Receive request is
submitted by limit of
reveive FIFO
7
N
RDREQ = 1?
Y
8 Setting of SIRDR register
Receive
Reading of receive data
N
Finish to transmit?
9
Y
"0" is set to RXE bit of SICTR register
Set to transmit disable
Finish to receive
End
Figure 20.10 Example of Receive Operation in Master
Rev.6.00 Mar. 27, 2009 Page 642 of 1036
REJ09B0254-0600