HD6417727BP160CV Datasheet, PDF (104/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
Addressing Instruction
Mode
Format
Indexed GBR @(R0, GBR)
indirect
Effective Address Calculation Method
Effective address is sum of register GBR and
R0 contents.
GBR
+
GBR + R0
Calculation
Formula
GBR + R0
R0
PC-relative @(disp:8, PC)
with
displacement
Effective address is PC with 8-bit displacement
disp added. After disp is zero-extended, it is
multiplied by 2 (word) or 4 (longword), according
to the operand size. With a longword operand,
the lower 2 bits of PC are masked.
Word:
PC + disp × 2
Longword:
PC&H'FFFFFFFC
+ disp × 4
PC
&^*
H'FFFFFFFC
+
disp
(zero-extended)
x
PC + disp × 2
or
PC&H'FFFFFFFC
+ disp × 4
2/4
*: With longword operand
Rev.6.00 Mar. 27, 2009 Page 46 of 1036
REJ09B0254-0600