HD6417727BP160CV Datasheet, PDF (908/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 27 I/O Ports
27.5 Ports F, M
Each pin has an input pullup MOS, which is controlled by Ports F, M Control Register (PFDR,
PMDR) in PFC.
27.5.1 Ports F, M Data Register (PFDR, PMDR)
Bit:
Initial value:
R/W:
Note: * Undefined
7
Px7DT
*
R
6
Px6DT
*
R
5
Px5DT
*
R
4
Px4DT
*
R
3
Px3DT
*
R
2
Px2DT
*
R
1
Px1DT
*
R
0
Px0DT
*
R
Ports F, M Data Register (PFDR, PMDR) is an 8-bit read register that stores data for pins PTx7 to
PTx0. Px7DT to Px0DT bit corresponds to PTx7 to PTx0 pin. When the pin function is general
input port, if the port is read, the corresponding pin level is read. Table 27.4 shows the function of
PFDR and PMDR.
PFDR and PMDR are initialized by a power-on reset. After initialization, the general input port
function (pullup MOS: on) is set as the initial pin function, and the corresponding pin levels are
read.
Table 27.4 Read/Write Operation of the Ports F, M Data Register (PFDR, PMDR)
PxnMD1 PxnMD0 Pin State
Read
Write
0
0
Other function H’00
Ignored (no affect on pin state)
1
Reserved* ⎯
⎯
1
0
Input (Pullup Pin state
Ignored (no affect on pin state)
MOS on)
1
Input (Pullup Pin state
Ignored (no affect on pin state)
MOS off)
Note: * Operation cannot be guaranteed when this bit it set to “reserved.”
(n = 0 to 7)
(x = F, M)
Rev.6.00 Mar. 27, 2009 Page 850 of 1036
REJ09B0254-0600