HD6417727BP160CV Datasheet, PDF (313/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 9 Power-Down Modes and Software Reset
9.7.3 Timing of Hardware Standby Mode
The timings of each pin in hardware standby mode are shown in figures 9.10 and 9.11.
CA pin is sampled by EXTAL2 (32.768 kHz). Hardware standby request is detected when two
continuous cycles go low in this clock.
Keep CA pin low during hardware standby mode.
The clock starts oscillation when the CA pin is set high after setting the RESETP pin low.
CKIO, CKIO2^*6
CA
RESETP
STATUS
Normal^*3
Standby^*2
*7
Reset^*1
0−10Bcyc^*4
2 Rcyc or more^*5
Notes: 1. Reset: HH (STATUS1 is high, STATUS0 is high)
2. Standby: LH (STATUS1 is low, STATUS0 is high)
3. Normal: LL (STATUS1 is low, STATUS0 is low)
4. Bcyc: Bus clock cycle
5. Rcyc: EXTAL2 (32.768 kHz) clock cycle
6. CKIO2 can be used at only clock modes 0,1 and 2.
7. Undefined
Figure 9.10 Hardware Standby Mode Timing
(CA = Low in Normal Operation)
Rev.6.00 Mar. 27, 2009 Page 255 of 1036
REJ09B0254-0600