HD6417727BP160CV Datasheet, PDF (579/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 17 Serial Communication Interface (SCI)
1
Serial
data
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data _bit bit
1
D₁
D₇ 0/1 1
Idling
(marking)
RDRF
FER
RXI interrupt
request generated
1 frame
Reads data with
the RXI interrupt
processing routine
and clears RDRF
bit to 0
ERI interrupt
request generated
by framing error
Figure 17.11 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
17.3.3 Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single serial
communication line. The processors communicate in the asynchronous mode using a format with
an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by a unique ID.
A serial communication cycle consists of an ID-sending cycle that identifies the receiving
processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from
data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it wants
to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit set to
1.
When they receive data with the multiprocessor bit set to 1, receiving processors compare the data
with their IDs. The receiving processor with a matching ID continues to receive further incoming
data. Processors with IDs not matching the received data skip further incoming data until they
Rev.6.00 Mar. 27, 2009 Page 521 of 1036
REJ09B0254-0600