HD6417727BP160CV Datasheet, PDF (845/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 25 LCD Controller
Bits 7, 3, and 2—Reserved
Bits 15 to 12—LCDC Power-On Sequence Period (ONC): Set the period from VEPWC
assertion to DON assertion in the power-on sequence of the LCD module in frame units.
This period is the (c) period in figures 25.4 to 25.7. For details on setting this register, see table
25.4. (The setting method is common for ONC, ONA, ONB, OFFD, OFFE, and OFFF.) 1 is to be
subtracted from the setting.
Bits 11 to 8—LCDC Power-Off Sequence Period (OFFD): Set the period from DON negation
to VEPWC negation in the power-off sequence of the LCD module in frame units.
This period is the (d) period in figures 25.4 to 25.7. 1 is to be subtracted from the setting.
Bit 6—VCPWC Pin Enable (VCPE): Sets whether or not to enable a power-supply control
sequence using the VCPWC pin.
Bit 6
VCPE
0
1
Description
Disabled: VCPWC pin is masked and fixed low
(Initial value)
Enabled: VCPWC pin output is asserted and negated according to the power-on or
power-off sequence
Bit 5—VEPWC Pin Enable (VEPE): Sets whether or not to enable a power-supply control
sequence using the VEPWC pin.
Bit 5
VEPE
0
1
Description
Disabled: VEPWC pin is masked and fixed low
(Initial value)
Enabled: VEPWC pin output is asserted and negated according to the power-on or
power-off sequence
Bit 4—DON Pin Enable (DONE): Sets whether or not to enable a power-supply control
sequence using the DON pin.
Bit 4
DONE
0
1
Description
Disabled: DON pin is masked and fixed low
Enabled: DON pin output is asserted and negated according to the power-on or power-
off sequence
(Initial value)
Rev.6.00 Mar. 27, 2009 Page 787 of 1036
REJ09B0254-0600