HD6417727BP160CV Datasheet, PDF (792/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 24 USB HOST Module
Register: HcCommandStatus
Bits
Reset R/W
0
0b
R/W
Offset: 08–0B
Description
HostControllerReset (HCR)
This bit is set by HCD to initiate the software reset of the host
controller. The system is moved to the UsbSuspend state in
which most of the operational registers are reset except for the
next state regardless of the functional state of the host
controller. For example, an access to the InterrupRouting field
in HcControl and without host bus are allowed. This bit is
cleared by the host controller upon completion of the reset
operation. This bit does not cause any reset to the route hub
and the next reset signal is not issued to the downstream port.
0: Cleared by the host controller at the completion of the reset
control
1: UsbSuspend state
Rev.6.00 Mar. 27, 2009 Page 734 of 1036
REJ09B0254-0600