HD6417727BP160CV Datasheet, PDF (95/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 2 CPU
16 bit
16 bit
8 bit
MOVS.W,
MOVS.L
39 32
A0G
MOVX.W MOVY.W
31
A1G
DSR
7
0
32 bit
16
A0
A1
M0
M1
X0
X1
Y0
Y1
LDB
XDB
YDB
MOVS.W,
MOVS.L
0
Figure 2.8 Connections of DSP Registers and Buses
The DSP unit has DSP status register (DSR). The DSR has conditions of the DSP data operation
result (zero, negative, and so on) and a DC bit which is similar to the T bit in the CPU. The DC bit
indicates the one of the conditional flags. A conditional DSP data processing instruction controls
its execution based on the DC bit. This control affects only the operations in the DSP unit; it
controls the update of DSP registers only. It cannot control operations in CPU, such as address
register updating and load/store operations. The control bit CS[2:0] specifies the condition to be
reflect to the DC bit.
The unconditional DSP type data operations, except PMULS, MOVX, MOVY and MOVS, update
the conditional flags and DC bit, but no CPU instructions, including MAC instructions, update the
DC bit. The conditional DSP type instructions do not update the DSR either.
DSR is assigned as a system register and load/store instructions are prepared as follows:
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
When DSR is read by the STS instructions, the upper bits (bit 31 to bit 8) are all 0.
Rev.6.00 Mar. 27, 2009 Page 37 of 1036
REJ09B0254-0600