HD6417727BP160CV Datasheet, PDF (673/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 20 Serial IO (SIOF)
Bit 15—Control Command Data Channel 0 Enable (CD0E)
Bit 15: CD0E
0
1
Description
Disable transmitting or receiving of control command of channel 0.
(Initial value)
Enable transmitting or receiving of control command of channel 0.
Bits 11 to 8—Control Command Data Assignment for Channel 0 (CD0A3 to CD0A0): The
slot assignment for control channel 0 in transmit and receive frames is specified from 0000(0:
initial value) to 1110(14) by this register. The receive data for control channel 0 is set in bits
SITC05 to SITC00 of SIRCR register. The receive data for control channel 0 is stored in bits
SIRC015 to SIRC00 in SIRCR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits CD0A3 to CD0A0.
Bit 7—Control Command Data Channel 1 Enable (CD1E)
Bit 7: CD1E
0
1
Description
Disable transmitting or receiving of control command of channel 1.
(Initial value)
Enable transmitting or receiving of control command of channel 1.
Bits 3 to 0—Control Command Data Assignment for Channel 1 (CD1A3 to CD1A0): The slot
assignment for control channel 1 in transmit and receive frames is specified from 0000(0: initial
value) to 1110(14) by this register. The receive data for control channel 1 is set in bits SIRC115 to
SIRC10 of SIRCR register.
Note: The operation of this LSI is unpredictable when setting 1111 in bits CD1A3 to CD1A0.
Rev.6.00 Mar. 27, 2009 Page 615 of 1036
REJ09B0254-0600