HD6417727BP160CV Datasheet, PDF (388/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 12 Bus State Controller (BSC)
Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT
signal has no effect if asserted in the T1 cycle or the first Tw cycle.
The WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with
respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge
is used..
However, the WAIT signal is ignored in the following three cases:
• When writing to an external address area using DMA 16-byte transfer in dual address mode
• When transferring data from a DACK-equipped external device to an external address area
using DMA 16-byte transfer in dual address mode
• During cache write-back access
Wait states inserted
by WAIT signal
T1
Tw
Tw
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
WAIT
BS
Figure 12.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal
WAITSEL = 1)
Rev.6.00 Mar. 27, 2009 Page 330 of 1036
REJ09B0254-0600