HD6417727BP160CV Datasheet, PDF (655/1098 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family/ SH7700 Series

Section 19 Serial Communication Interface with FIFO (SCIF)
Error processing
No
ER = 1?
Yes
Receive error processing
No
BRK= 1?
1. Whether a framing error or parity error has
occurred in the receive data read from
SCFRDR2 can be ascertained from the FER
and PER bits in SCSSR2.
2. When a break signal is received, receive data
is not transferred to SCFRDR2 while the BRK
flag is set. However, note that the last data in
SCFRDR2 is H'00 and the break data in which
a framing error occurred is stored.
Break processing
No
DR= 1?
Yes
Read receive data in SCFRDR2
Clear DR, ER, BRK flags in
SCSSR2 to 0
End
Figure 19.9 Sample Serial Reception Flowchart (2)
Rev.6.00 Mar. 27, 2009 Page 597 of 1036
REJ09B0254-0600